用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:AI推論、機器人、AI PC、AI Server
功能:INT8/FP16、Transformer、矩陣加速,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:TSMC 28nm / 16nm / 7nm / 5nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影像運算、AI視覺、3D顯示、影片編解碼
功能:Shader、Video Codec、Display、AI Vision,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:28nm / 16nm / 12nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:IoT、家電、工控、車用控制
功能:RISC-V Controller、GPIO、UART、SPI、I2C,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:180nm / 110nm / 65nm / 40nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:機器人主控、感測融合、馬達控制
功能:CPU + NPU + DSP + Motor Control,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:語音辨識、降噪、音訊處理
功能:Echo Cancel、Noise Reduction、Wake Word,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:加密、安全啟動、金鑰管理
功能:AES、SHA、RSA/ECC、TRNG、Secure Boot,可依客戶需求整合 RTL IP
功能效能:Level 2,預估效能 20~400 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:相機、車用影像、機器視覺
功能:HDR、Demosaic、3A、Noise Reduction,可依客戶需求整合 RTL IP
功能效能:Level 3,預估效能 30~600 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:影片編解碼、串流、AI TV
功能:H.264/H.265/AV1、Scaler、Overlay,可依客戶需求整合 RTL IP
功能效能:Level 4,預估效能 40~800 TOPS / 等級化客製
適合製程:28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:資料搬移、SoC 高速傳輸
功能:DMA、AXI、Wishbone、AHB Bridge,可依客戶需求整合 RTL IP
功能效能:Level 5,預估效能 50~1000 TOPS / 等級化客製
適合製程:65nm / 40nm / 28nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |
用途:DDR、SRAM、Flash、Cache控制
功能:DDR Controller、SRAM Controller、ECC,可依客戶需求整合 RTL IP
功能效能:Level 1,預估效能 10~200 TOPS / 等級化客製
適合製程:40nm / 28nm / 16nm / 7nm
使用說明:適合從 IC1000 RTL Library 自動選 IP,建立 SoC、ASIC、FPGA Prototype、Tape-Out Package。
價格:Quotation
製造檔案完整度:38%
| RTL / Verilog | ready |
| Testbench | ready |
| Synthesis Script | ready |
| SDC Timing Constraint | ready |
| LEF / DEF | pending_pnr |
| GDSII | pending_pnr |
| LIB | pending_characterization |
| SPEF | pending_extraction |
| DRC Report | pending_foundry_rule |
| LVS Report | pending_layout_verify |
| BOM | ready |
| Datasheet | ready |
| Tape-Out Checklist | review_required |
| License Status | review_required |